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| CY24206 MediaClockTM DTV, STB Clock Generator Features * Integrated phase-locked loop (PLL) * Low-jitter, high-accuracy outputs * 3.3V operation * Available in 16-pin TSSOP Package Part Number CY24206-1 Outputs 3 Input Frequency 27 MHz Benefits * Internal PLL with up to 400-MHz internal operation * Meets critical timing requirements in complex system designs * Enables application compatibility Output Frequency Range 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) CY24206-2 4 27 MHz CY24206-3 4 27 MHz CY24206-4 4 27 MHz Logic Block Diagram XIN XOUT P OSC. Q VCO OUTPUT MULTIPLEXER AND DIVIDERS CLK1 CLK2 REFCLK FS0 FS1 FS2 OE CLK3 (-2, -3,-4) PLL Pin Configurations CY24206-1 16-pin TSSOP XIN VDD AVDD OE AVSS VSSL CLK1 CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FS2 FS1 VSS N/C VDDL VDDL VDD AVDD AVSS VSS VSSL CY24206-2,3,4 16-pin TSSOP XOUT XIN VDD AVDD OE AVSS VSSL CLK1 CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT FS2 FS1 VSS CLK3 VDDL FS0 REFCLK FS0 REFCLK Cypress Semiconductor Corporation Document #: 38-07451 Rev. *B * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised September 27, 2004 CY24206 Frequency Select Options FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CLK1 (-1,-2) 81 81.081 74.175 74.250 81 81.081 74.175 74.250 CLK1 (-3,-4) 81 81.081 74.17582 74.25 81 81.081 74.1758 74.25 CLK2 27 (CLK1/3) 27.027 (CLK1/3) 24.725 (CLK1/3) 24.75 (CLK1/3) 27 27 27 27 CLK3 (-2, -3,-4) 27 (CLK1/3) 27.027 (CLK1/3) 74.17582 (CLK1) 74.25 (CLK1) 27 (CLK1/3) 27.027 (CLK1/3) 74.175 (CLK1) 74.25 (CLK1) REFCLK 27 27 27 27 27 27 27 27 Units MHz MHz MHz MHz MHz MHz MHz MHz Pin Description Name XIN VDD AVDD OE AVSS VSSL CLK1 (-1,-2) CLK1 (-3,-4) CLK2 REFCLK FS0 VDDL N/C (-1) CLK3 (-2,-3,-4) VSS FS1 FS2 XOUT Pin Number 1 2 3 4 5 6 7 7 8 9 10 11 12 12 13 14 15 16 Reference Crystal Input. Voltage Supply. Analog Voltage Supply. Output Enable, weak internal pull-up. 0 = outputs off, 1 = outputs on. Analog Ground. VDDL Ground. 81-/81.081-/74.175-/74.250-MHz Clock Output (frequency selectable). 81-/81.081-/74.17582-/74.25-MHz Clock Output (frequency selectable). 27-/27.027-/24.725-/24.75-MHz Clock Output (frequency selectable). Reference Clock Output. Frequency Select 0, weak internal pull-up. Voltage Supply. No Connect. 27-/27.027-/74.175-/74.25-MHz Clock Output (frequency selectable). Ground. Frequency Select 1, weak internal pull-up. Frequency Select 2, weak internal pull-up. Reference Crystal Output. Description Document #: 38-07451 Rev. *B Page 2 of 6 CY24206 Absolute Maximum Conditions Parameter VDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Electrostatic Discharge AVSS - 0.3 2 Min. -0.5 Max. 7.0 7.0 125 AVDD + 0.3 Unit V V C V kV Recommended Operating Conditions Parameter VDD/AVDDL/VDDL TA CLOAD fREF Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency 27 Min. 3.135 0 Typ. 3.3 Max. 3.465 70 15 Unit V C pF MHz DC Electrical Specifications Parameter[1] IOH IOL IIH IIL VIH VIL IVDD IVDDL RUP Name Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Pull-up resistor on Inputs Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VIH = VDD VIL = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current VDD = 3.14 to 3.47V, measured VIN = 0V 100 Min. 12 12 - - 0.7 0.3 25 20 150 Typ. 24 24 5 - 10 50 Max. Unit mA mA A A VDD VDD mA mA k AC Electrical Specifications Parameter[1] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. CLK1, CLK2 Peak-Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 3 Max. 55 Unit % V/ns V/ns ps ms Test and Measurement Set-up VDDs 0.1 F DUT Outputs CLOAD GND Note: 1. Not 100% tested. Document #: 38-07451 Rev. *B Page 3 of 6 CY24206 Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definitions t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Ordering Information Ordering Code CY24206ZC-2 CY24206ZC-2T CY24206ZC-3 CY24206ZC-3T CY24206ZC-4 CY24206ZC-4T Lead Free CY24206ZXC-4 CY24206ZXC-4T Z16 Z16 Z16 Z16 Z16 Z16 Z16 Z16 Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Package Type 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP Operating Range Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Package Name 16-Pin TSSOP - Tape and Reel Commercial 16-Pin TSSOP - Tape and Reel Commercial 16-Pin TSSOP - Tape and Reel Commercial 16-Pin TSSOP Commercial 16-Pin TSSOP - Tape and Reel Commercial Document #: 38-07451 Rev. *B Page 4 of 6 CY24206 Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07451 Rev. *B Page 5 of 6 CY24206 Document History Page Document Title: CY24206 MediaClockTM DTV, STB Clock Generator Document Number: 38-07451 REV. ** *A *B ECN NO. 120901 123046 270029 Issue Date 12/10/02 03/03/03 See ECN Orig. of Change CKN CKN RGL New data sheet Added -4 to data sheet Removed Preliminary Added Lead-free devices for -4 Description of Change Document #: 38-07451 Rev. *B Page 6 of 6 |
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